1. Field of the Invention
The present invention relates to interconnect integration technology. More specifically, the present invention relates to methylated oxide-type hardmasks for patterning interlayer dielectrics in integrated circuit device fabrication.
2. Description of the Related Art
Integration of multilevel interconnects becomes increasingly important with ever increasing demands for device miniaturization and speed. In fact, with sub-0.25 .mu.m geometries, interconnect capacitance is much larger than transistor capacitance. A reduction of the interconnect capacitance decreases RC and in turn, delay, thereby in creasing device speed.
Efforts to improve device performance include reducing the dielectric constant of interlayer dielectrics and the electrical resistance of interconnects, thereby reducing the wiring delay. Ikeda, et al., I.E.E.E. Inter. Interconnect Technology Conf. (1998) p. 131, describe a low k polymeric dielectric with a Cu-damtascene structure. The polymeric dielectric (AlClied Signal's FLARE.TM.) was spin coated on undoped silicon glass (USG). The polymeric dielectric was then patterned through an overlying USG hardmask. Copper lines were formed by sputtering and CMP. Ikeda, et al. reported advantageous use of USG in achieving simultaneous resist ashing and etching of the polymeric dielectric as well as anisotropic O.sub.2 RIE etching. In addition, Ikeda, et al. reported relatively decreased wiring resistance of copper metallization formed in the polymeric dielectric with increasing metallization width.
However, certain disadvantages attend. As those of skill in the art will appreciate, conventional processing to put a USG hardmask on a polymeric dielectric requires removal of the wafer from spin track equipment after formation of a polymeric dielectric to a different machine in order to create the hardmask. In addition, conventional USG hardmasks do not adhere well to a polymeric interlayer dielectric, which affects subsequent wafer processing.